An integrated circuit memory is commonly implemented as a plurality of rows in one or more blocks, crossing a plurality of bit line pairs. Memory cells are located at intersections of rows and bit line pairs, and are accessed when the row and the bit line pair on which they are located are selected. Rows and bit line pairs are selected by row and column decoding of the address, respectively. Additionally, block decoding may select between two or more memory blocks.
A desirable feature for integrated circuit memories is row redundancy. In an integrated circuit memory with row redundancy, a manufacturing defect in a particular row can be cured by using a redundant row in place of the defective row. Two operations are necessary to replace the defective row with the redundant row. First, the defective row must be deselected. Second, a redundant row must be assigned the address of the defective row, so that it functions in place of the defective row.
The defective row deselection and redundant row assignment may be implemented using fuses. A fuse element is typically a segment of polysilicon lacking an overlying layer of passivation. Prior to packaging, in which the integrated circuit still resides on a wafer and is being tested by a prober, a defective row can be deselected by blowing a fuse connected to the row. The fuse is blown by applying a high-energy laser light focused to the approximate height of the polysilicon.
Row deselection may be achieved by placing fuses between the output signals of the row decoder and the row select lines. See, for example, Isobe et al. in U.S. Pat. No. 4,587,638 entitled "Semiconductor Memory Device". However, placing the fuses on the row select lines results in certain disadvantages. As semiconductor memories become larger, the row select lines must select more memory cells, and therefore are longer. The longer lines are more heavily loaded capacitively, and therefore an increase in resistance through the fuse increases the time constant of the row select line, and slows down the rise time of the row select lines and hence the access time of the memory. In very high speed memories in particular, this extra delay caused by placing fuses between the row decoder and the row select lines can make row redundancy infeasible.